AIDS307/AIML307
Computer Organization & Architecture
B.Tech (Artificial Intelligence & Machine Learning) • Semester 5
Overview
This course enables the students to understand the principles of computer organization and the basic architectural concepts. It begins with basic organization, design, and programming of a simple digital computer and introduces simple register transfer language to specify various computer operations. Topics include computer arithmetic, instruction set design, microprogrammed control unit, pipelining and vector processing, memory organization and I/O systems, and multiprocessors.
Course Syllabus
Unit I
Register Transfer Language: Register transfer language, bus and memory transfer, bus architecture using multiplexer and tri-state buffer, micro-operation: arithmetic, logical, shift micro-operation with hardware implementation, arithmetic logic shift unit.
Computer Organization and Design: Instruction codes, general computer registers with common bus system, computer instructions: memory reference, register reference, input-output instructions, timing and control, instruction cycle, input-output configuration, and interrupt cycle.
Levels of programming languages: Machine language, Assembly language, High level language.
Unit II
Central processing Unit: Introduction, general register organization, stack organization, instruction format, addressing modes.
Overview of GPU, CPU vs GPU computing difference.
Memory Hierarchy: Introduction, basics of cache, measuring and improving of cache performance, cache memory: associative mapping, direct mapping, set-associative mapping, cache writing and initialization, virtual memory, common framework for memory hierarchies.
Case study of PIV and AMD opteron memory hierarchies.
Unit III
Parallel Computer Models: The state of computing, classification of parallel computers, multiprocessors and multicomputers, multivector and SIMD computers.
Program and Network Properties: conditions of parallelism, data and resource dependences, hardware and software parallelism, program partitioning and scheduling, grain size and latency, program flow mechanisms, control flow versus data flow, data flow Architecture, demand driven mechanisms, comparisons of flow mechanisms.
Unit IV
Pipelining: Introduction to Flynn's classification, arithmetic pipeline, instruction pipeline, pipeline conflict and hazards, RISC pipeline, vector processing.
Arithmetic for Computers: Unsigned, signed 1's, 2's compliment notations, addition, subtraction, multiplication and division (hardware implementation), CPU performance and its factors, evaluating performance of CPU.
Unit-wise Notes & Study Material
Notes coming soon. We're working on adding comprehensive study materials.